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| 16-bit, 1.2 msps cmos, sigma-delta adc ad7723 rev. c in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 461. 31 13 ? 2005 a n alog de vices, i n c. al l r i ght s r e ser v ed . features 16-bit -? adc 1.2 msps outp ut word rate 32/16 overs a mpling ratio low-pass and band-pass digi tal filt er linear phase on-chip 2.5 v voltage referenc e standby mode flexible parall el or serial inte rface crystal oscillat o r single 5 v supp ly general description the ad7723 is a co m p lete 16-b i t, sig m a-de l t a ad c. the p a r t op e r a t e s f r om a 5 v su p p ly . t h e ana l o g in p u t is c o n t i n u o u sly s a m p le d , e l imina t in g t h e n e e d fo r a n ext e r n al s a m p le-and-h o ld. the m o d u la t o r o u t p ut is p r o c ess e d b y a f i ni t e i m p u ls e r e s p o n s e (fir) dig i t a l f i l t er . the o n -chi p f i l t er in g com b i n e d wi t h a hig h o v ers a m p li n g ra t i o r e d u ces t h e ext e r n al a n t i al ias r e q u ir emen t s t o fi r s t o r d e r i n m o s t c a s e s . t h e d i g i t a l fi l t e r fr e q u e n c y r e s p o n se ca n be p r og ra mm e d t o be ei t h er lo w-p a s s o r band-p a s s . the ad7723 p r o v ides 16-b i t p e r f o r ma n c e f o r in p u t b a ndwid ths u p t o 460 kh z a t a n o u t p u t w o r d ra t e u p t o 1.2 mh z. th e s a m p le ra te , f i l t er co r n er f r eq uen c ies, and o u t p u t w o r d ra te a r e s e t b y t h e cr ys tal os cil l a t o r o r ext e r n al c l o c k f r eq uen c y . da t a can b e r e ad f r o m the de vice in ei t h er s e r i al o r p a ral l e l f o r m a t . a s t er eo m o de al lo ws da ta f r o m tw o de vices t o s h a r e a sin g le s e r i al da t a lin e . al l in t e r f ace m o des o f f e r e a sy , hig h s p e e d co nn e c t i o n s to m o der n dig i t a l sig n a l p r o c ess o r s . func tio n a l block di agram agnd av dd dgnd vin(+) vin(?) ref2 xtal clkin mo d e 1 stby sync cfmt/ r d dgnd/ drdy dgnd/ db1 doe/ db4 sfmt/ db5 fsi / db6 sco/ db7 modulator fir filter xtal clock ad7723 dgnd/ db2 dgnd/ db3 sdo/ db8 dgnd/db0 control logic dv dd /c s mo d e 2 half_pwr uni dgnd/db14 dgnd/db15 scr/db13 sldr/db12 slp/db11 tsi/db10 fso/db9 xtal_off 2.5v reference ref1 dv dd 01186- 001 fi g u r e 1 . the p a r t p r o v ides a n o n -chi p 2. 5 v r e fer e n c e . a l t e r n a t i v e l y , an e x te r n a l re f e re n c e c a n b e u s e d . a p o w e r - do w n m o de r e d u ces t h e i d le p o w e r c o n s um pt io n t o 200 w . the ad7723 is a v a i la b l e in a 44 -lead m q fp p a c k a g e and is s p e c if ie d o v er t h e i n d u s t r i al te m p era t ur e ra n g e f r o m C40c t o +85c. t w o i n put mo d e s are pro v i d e d , a l l o w i ng b o t h u n i p ol ar an d b i p o la r in p u t ran g es.
ad7723* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. evaluation kits ? ad7723 evaluation board documentation application notes ? an-202: an ic amplifier users guide to decoupling, grounding, and making things go right for a change ? an-283: sigma-delta adcs and dacs ? an-311: how to reliably protect cmos circuits against power supply overvoltaging ? an-388: using sigma-delta converters-part 1 ? an-389: using sigma-delta converters-part 2 ? an-397: electrically induced damage to standard linear integrated circuits: data sheet ? ad7723: 16-bit, 1.2 msps, cmos sigma delta converter data sheet tools and simulations ? sigma-delta adc tutorial reference materials technical articles ? delta-sigma rocks rf, as adc designers jump on jitter ? ms-2210: designing power supplies for high speed adc ? part 1: circuit suggestions using features and functionality of new sigma-delta adcs ? part 2: circuit suggestions using features and functionality of new sigma-delta adcs design resources ? ad7723 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad7723 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified. ad7723 rev. c | page 2 of 32 table of contents specifications ..................................................................................... 3 timing specifications ....................................................................... 6 absolute maximum ratings .......................................................... 10 esd caution ................................................................................ 10 pin configuration and function descriptions .......................... 11 ter mi nolo g y .................................................................................... 14 typical performance characteristics ........................................... 15 circuit description ......................................................................... 18 applying the ad7723 .................................................................... 20 analog input range ................................................................... 20 analog input ............................................................................... 20 driving the analog inputs ........................................................ 20 applying the reference .............................................................. 21 clock generation ....................................................................... 22 system synchronization ................................................................ 23 data interfacing .............................................................................. 24 parallel interface ......................................................................... 24 serial interface ................................................................................ 25 two-channel multiplexed operation ..................................... 25 serial interface to dsps ................................................................. 27 ad7723 to adsp-21xx interface ............................................. 27 ad7723 to sharc interface .................................................... 27 ad7723 to dsp56002 interface ............................................... 27 ad7723 to tms320c5x interface ............................................ 27 grounding and layout .................................................................. 28 outline dimensions ....................................................................... 29 ordering guide .......................................................................... 29 revision history 5/05rev. b to rev. c changes to format .............................................................universal changes to figure 6.......................................................................... 8 changes to system synchronization ............................................ 23 updated outline dimensions ....................................................... 29 changes to the ordering guide.................................................... 29 10/03rev. a to rev. b changes to ordering guide ............................................................ 8 outline dimensions updated ....................................................... 23 9/02data sheet changed from rev. 0 to rev. a new tpcs 1 and 2 added ............................................................. 13 edits to figures 17 and 18 ............................................................. 18 outline dimensions updated....................................................... 23 ad7723 rev. c | page 3 of 32 specifications 1 av dd = dv dd = 5 v 5%; agnd = agnd1 = agnd2 = dgnd = 0 v; f clkin = 19.2 mhz; ref2 = 2.5 v; t a = t min to t max , unless otherwise noted. table 1. b version parameter test conditions/comments min typ max unit dynamic specifications 2 , 3 half_pwr = 0 to 1 f clkin = 10 mhz when half_pwr = 1 decimate by 32 bipolar mode signal to noise full power 2.5 v reference 87 90 db 3 v reference 88.5 91 db half power 86.5 89 db total harmonic distortion 4 ?96 ?90 db spurious-free dynamic range 4 2.5 v reference ?92 db 3 v reference ?90 db unipolar mode signal to noise 87 db total harmonic distortion 4 ?89 db spurious-free dynamic range 4 ?90 db band-pass filter mode bipolar mode signal to noise 76 79 db decimate by 16 bipolar mode signal to noise measurement bandwidth = 0.383 f o 2.5 v reference 82 86 db 3 v reference 83 87 db signal to noise measurement bandwidth = 0.5 f o 78 81.5 db total harmonic distortion 4 2.5 v reference ?88 db spurious-free dynamic range 4 3 v reference ?86 db 2.5 v reference ?90 db 3 v reference ?88 db unipolar mode signal to noise measurement bandwidth = 0.383 f o 84 db signal to noise measurement bandwidth = 0.5 f o 81 db total harmonic distortion 4 ?89 db digital filter response low-pass decimate by 32 0 khz to f clkin /83.5 0.001 db f clkin /66.9 ?3 db f clkin /64 ?6 db f clkin /51.9 to f clkin /2 ?90 db group delay 1293/2 f clkin settling time 1293/f clkin ad7723 rev. c | page 4 of 32 b version parameter test conditions/comments min typ max unit low-pass decimate by 16 0 khz to f clkin /41.75 0.001 db f clkin /33.45 ?3 db f clkin /32 ?6 db f clkin /25.95 to f clkin /2 ?90 db group delay 541/2 f clkin settling time 541/f clkin band-pass decimate by 32 f clkin /51.90 to f clkin /41.75 0.001 db f clkin /62.95, f clkin /33.34 ?3 db f clkin /64, f clkin /32 ?6 db 0 khz to f clkin /83.5, f clkin /25.95 to f clkin /2 ?90 db group delay 1293/2 f clkin settling time 1293/f clkin output data rate, f o decimate by 32 f clkin /32 decimate by 166 f clkin /16 analog inputs full-scale input span vin(+) ? vin(?) bipolar mode 4/5 v ref2 v unipolar mode 0 8/5 v ref2 v absolute input voltage vin(+) ? vin(?) agnd av dd v input sampling capacitance 2 pf input sampling rage, f clkin 19.2 mhz clock clkin duty ratio 45 55 % reference ref1 output resistance 3 k? using internal reference ref2 output voltage 2.39 2.54 2.69 v ref2 output voltage drift 60 ppm/c using external reference ref2 input impedance ref1 = agnd 4 k? ref2 external voltage range 1.2 2.5 3.15 v static performance resolution 16 bits differential nonlinearity guaranteed monotonic 0.5 1 lsb integral nonlinearity 2 lsb dc cmrr 80 db offset error 20 mv gain error 5 0.5 % fsr logic inputs (excluding clkin) v inh , input high voltage 2.0 v v inl , input high voltage 0.8 v clock input (clkin) v inh , input high voltage 3.8 v v inl , input high voltage 0.4 v all logic inputs i in , input current v in = 0 v to dv dd 10 a c in , input capacitance 10 pf ad7723 rev. c | page 5 of 32 b version parameter test conditions/comments min typ max unit logic ouputs v oh , output high voltage |i out | = 200 a 4.0 v v ol , output low voltage |i out | = 1.6 ma 0.4 v power supplies av dd 4.75 5.25 v i avdd half_pwr = logic low 50 60 ma half_pwr = logic high 25 33 ma dv dd 4.75 5.25 v i dvdd half_pwr = logic low 25 35 ma half_pwr = logic high 15 20 ma power consumption 6 standby mode 200 w 1 operating temperature range is ?40c to +85c (b: version). 2 typical values for snr apply for parts soldered directly to the pcb ground plane. 3 dynamic specifications apply for input signal frequencies from dc to 0.0240 f clkin in decimate by 16 mode and from dc to 0.0120 f clkin in decimate by 32 mode. 4 when using the internal reference, thd and sfdr specifications apply only to input signals above 10 khz with a 10 f decouplin g capacitor between ref2 and agnd2. at frequencies below 10 khz, thd degrades to 84 db and sfdr degrades to 86 db. 5 gain error excludes reference error. 6 clkin and digital inputs static and equal to 0 or dv dd . ad7723 r e v. c | pa ge 6 o f 3 2 timing specifications av dd = d v dd = 5 v 5% ; a g nd = a g nd1 = d g nd = 0 v ; f clkin = 19.2 mh z; c l = 50 pf; s f mt = log i c lo w o r hig h , cfmt = log i c lo w or h i g h ; t a = t min to t max , unles s o t her w is e no t e d . table 2. p a r a m e t e r s y m b o l m i n t y p m a x u n i t clkin frequency f clk 1 1 9 . 2 m h z clkin period ( t cl k C 1/f clk ) t 1 0 . 0 5 2 1 s clkin low pulse wid t h t 2 0.45 t 1 0.55 t 1 clkin high puls e width t 3 0.45 t 1 0.55 t 1 clkin rise time t 4 5 n s clkin fall t ime t 5 5 n s fsi setup time t 6 0 5 n s fsi hold time t 7 0 5 n s fsi high time 1 t 8 1 t clk clkin to sco d e lay t 9 2 5 4 0 n s sco period 2 , scr = 1 t 10 2 t clk sco period 2 , scr = 0 t 10 1 t clk sco t r ansition to fso high dela y t 11 0 5 n s sco t r ansition to fso low dela y t 12 0 5 n s sco t r ansition to sdo valid delay t 13 5 1 2 n s sco t r ansition f r om fsi 3 t 14 6 0 t clk + t 2 sdo enable delay time t 15 5 2 0 n s sdo disabl e del a y t ime t 16 5 2 0 n s drdy high time 2 t 17 2 t clk conversi on tim e 2 (refer to table 3 and table 4) t 18 1 6 / 3 2 t clk clkin to drdy trans i tio n t 19 3 5 5 0 n s clkin to da ta valid t 20 2 0 3 5 n s cs / rd setup time to clkin t 21 0 n s cs / rd hold time to clkin t 22 2 0 n s data access tim e t 23 2 0 3 5 n s bus relinquis h t ime t 24 2 0 3 5 n s sync input puls e width t 25 1 t clk sync low time before clkin rising t 26 0 n s drdy high delay after rising sync t 27 2 5 3 5 n s drdy low delay after sync low t 28 2 0 4 9 t clk 1 fso pu ls es a r e ga t e d by t h e r e lea s e of fsi (g oi n g l o w). 2 gua r a n t eed by des i gn . 3 fra m e syn c i s i n i t i a t e d on t h e fa l l i n g e d ge of cl kin . i ol 1.6ma 1.6v c l 50pf to output pin i oh 200 a 01186-002 f i g u re 2. l o ad ci r c uit f o r tim i ng spec i f ic at ions ad7723 r e v. c | pa ge 7 o f 3 2 clkin fsi sco 2.3v t 4 t 5 t 7 t 6 t 9 t 3 t 2 t 1 t 10 t 9 t 8 0.8v 01186-003 f i gure 3. s e r i a l m o de tim i ng fo r c l o c k input, f r a m e s y n c input, and s e ri al cl ock o u tput clkin fsi ( sfmt = 1) sco (c fmt = 0) fso ( sfmt = 0) fso ( sfmt = 1) sdo 32 clkin cycles t 8 t 11 t 12 t 13 t 14 t 11 d15 d14 d13 d2 d1 d0 d15 d14 01186- 004 f i gure 4. s e r i a l m o de 1: tim i ng fo r f r a m e s y n c input, f r a m e s y nc o u tput, s e ria l clo c k o u tput, a n d seri al d a ta o u tput (see t a ble 3 for c o ntr o l inp u ts, t s i = doe) d2 d1 d0 d15 d14 d13 d12 d11 d5 d4 d3 d2 d1 d0 d15 d14 t 8 t 11 t 12 t 13 t 14 32 clkin cycles clkin fsi sco ( c fmt = 0) fso sdo 01186-005 f i gure 5. s e r i a l m o de 2: tim i ng fo r f r a m e s y n c input, f r a m e s y nc o u tput, s e ria l clo c k o u tput, a n d seri al d a ta o u tput (see t a ble 3 for c o ntr o l inp u ts, t s i = doe) ad7723 r e v. c | pa ge 8 o f 3 2 t 11 t 12 t 13 t 14 clkin fsi sco ( c fmt = 0) fso sdo t 8 01186- 006 d15 d0 d1 d2 d14 d0 d1 d2 d3 d15 d14 d1 d2 d0 d3 d13 d13 d3 d15 32 clkin cycles 16 clkin cycles 16 clkin cycles f i gure 6. s e r i a l m o de 3: tim i ng fo r f r a m e s y n c input, f r a m e s y nc o u tput, s e ria l clo c k o u tput, a n d seri al d a ta o u tput (see t a ble 3 for c o ntr o l inp u ts, t s i = doe) table 3. serial interface (mo d e1 = 0, mo de2 = 0) c o n t r o l i n p u t s s e r i a l m o d e decima ti on rati o (s ldr ) digita l filt er m o de (slp) sco freque ncy (scr) o u t p u t d a t a r a t e s l d r s l p s c r 1 3 2 l o w p a s s f clk i n f clk i n / 3 2 1 1 0 1 3 2 b a n d p a s s f clk i n f clk i n / 3 2 1 0 0 2 3 2 l o w p a s s f clk i n / 2 f clk i n / 3 2 1 1 1 2 3 2 b a n d p a s s f clk i n / 2 f clk i n / 3 2 1 0 1 3 1 6 l o w p a s s f clk i n f clk i n / 1 6 0 1 0 table 4. parallel interface c o n t r o l i n p u t s digita l filt er m o de decima ti on rati o o u t p u t d a t a r a t e m o d e 1 m o d e 2 band pass 32 f clk i n / 3 2 0 1 low pass 32 f clk i n / 3 2 1 0 low pass 16 f clk i n / 1 6 1 1 t 16 t 15 doe sdo 01186-007 f i gure 7. s e r i a l m o de tim i ng fo r d a t a o u tput e n able and s e ri al d a ta o u tput ad7723 r e v. c | pa ge 9 o f 3 2 t 19 t 20 word n word n ? 1 word n + 1 t 18 t 17 t 19 clkin drdy db0 ?db15 01186-008 f i gu r e 8 . p a r a l l e l mo de rea d t i m i n g , cs and rd t i ed l o gi c l o w t 18 t 19 t 24 t 22 t 21 t 22 t 23 t 21 t 19 valid data clkin dr dy rd / c s db0?db15 01186-009 f i gu r e 9 . p a r a l l e l mo de rea d t i m i n g , cs = rd t 26 t 27 t 25 t 28 clkin sync drdy 01186-010 f i g u re 10. sync ti ming ad7723 rev. c | page 10 of 32 absolute maximum ratings t a = 2 5 c , u n l e ss ot he r w i s e no t e d. table 5. p a r a m e t e r r a t i n g dv dd to dgnd ?0.3 v to +7 v av dd , av dd1 to a g nd ?0.3 v to +7 v av dd , av dd1 to dv dd ?1 v to +1 v agnd, agn d 1 t o dgnd ? 0.3 v to +0.3 v digital inputs to dgnd ?0.3 v to dv dd + 0.3 v digital outputs to dgnd ?0.3 v to dv dd + 0.3 v vin (+), vin ( ?) t o agnd ?0.3 v to av dd + 0.3 v ref1 to ag nd ?0.3 v to av dd + 0.3 v ref2 to ag nd ?0.3 v to av dd + 0.3 v operating temperature range ?40c to +85c storage temperature range ?65c to +150c junction tempe r ature 150c ja thermal imp e dance 95c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im pl ie d . e x p o sur e t o a b s o l u te max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . esd caution esd (electrostatic discharge) sensitive device. ele c tr ostatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharg e wit h out detection. althou gh this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity. ad7723 rev. c | page 11 of 32 pin conf iguration and fu nction descriptions 12 13 1 4 1 5 1 6 1 7 1 8 1 9 20 21 2 2 3 4 5 6 7 1 2 10 11 8 9 40 3 9 3 8 41 42 43 4 4 3 6 35 34 37 pin 1 identifier top view (not to scale) 29 30 31 32 27 28 25 26 23 24 33 scr/db13 dgnd/db14 doe / db4 dgnd/db15 s f mt/db5 dv dd /c s fs i/db6 sync s c o/db7 dgnd dv dd stby s d o/db8 av dd fs o/db9 clkin ts i/db1 0 xta l slp/d b 1 1 xta l _off s l dr/db1 2 half_pwr agnd agnd dgnd/db2 dgnd/db1 dgnd/db0 cfmt/r d dgnd/ drdy dgnd mode2 mode1 agnd1 agnd1 av dd1 av dd agnd uni ref2 vin ( ?) vin ( + ) re f1 agnd2 ad7723 dgnd/db3 01186-011 f i gure 11. 44-l ead mqfp ta ble 6. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic description 6, 28 dgnd ground reference for digital circuitry. 8, 7 mode1/mode2 mode control inputs . the mode 1 and mode2 pi ns cho o se either parallel or s e rial data interface operation and select the o p erating mode for the digital fi lter in para llel m o de. see table 3 and table 4. 9, 10 agnd1 digital logic power suppl y ground for the analog modulator. 1 1 a v dd1 digital logic power supply volt age for the analog modulator. 1 2 c l k i n clock in put. an external c l oc k s o urce can be a p plie d directly to this pin with xtal_off tied hig h . alternatively, a parallel re son a n t fundamental fr eq uency crystal, in pa rallel with a 1 m? resistor, can be conne cted betweenthe xtal pin and the clkin pin with xt al_off tied low. external cap a ci tors are then required from the clki n and xtal pins to ground. consult the cr ystal manufacturers recommendation for the load capacitors. 13 xtal input to crystal oscill ator amplifier. if an external clock is used, xtal should be tied to ag nd1. 1 4 x t a l _ o f f oscillator enable input. a logic high d i sable s th e crystal osci llat o r amplif ier to allow use of an external clock source. se t low when usi n g an external crystal between t h e clkin and x t al pins. 1 5 h a l f _ p w r when set high, the power dissip ation is reduced by approximate ly one-ha lf, and a maximum clk i n frequency of 10 mhz applies. 16, 18, 25 agnd power supply g r ound for the a n alog modulator. 17, 26 av dd positive power s u pply voltage for the analog modulator. 19 vin(?) negative terminal of th e differential analog input. 20 vin(+) positive terminal of th e differential analog input. 2 1 r e f 1 reference output. ref1 connects through 3 k? to the o utput of the internal 2.5 v reference and to a buffer amplifier that drives the -? modulator. 22 agnd2 power supply ground return to the refere nce circuitry, ref2, of the analog modulator. 2 3 r e f 2 reference input. ref2 connects to the output of an internal buff er amplif ier that drives the -? modulator. when ref2 is used as an input, ref1 must be connect ed to agn d to disable the internal buffer amplifier. 2 4 u n i analog input range select input. t h e uni pin selects th e anal og input range for either bipo lar or unipolar operatio n . a log i c high input sel e cts unipol ar op eration and a lo gic low se lects b i pola r operati on . 27 stby standby logic i n put. a logic high sets the ad7723 into the power-down state. ad7723 rev. c | page 12 of 32 pin no. mnemonic description 29 sync synchronization logic input. when using more than one ad7723 operated from a common master clock, sync allows each adc to simultaneously sample its an alog input and update its output register. a rising edge resets the ad7723 digital filter sequencer counter to 0. when the rising edge of clkin senses a logic low on sync, the reset state is released. because the digital filter and sequencer are completely reset during this action, sync pulses cannot be applied continuously. 39 dv dd digital power supply voltage; 5 v 5%. table 7. parallel mode pin function descriptions pin no. mnemonic description 1 dgnd/db2 data output bit. 2 dgnd/db1 data output bit. 3 dgnd/db0 data output bit (lsb). 4 cfmt/ rd read logic input. us ed in conjunction with cs to read data from the parallel bu s. the output data bus is enabled when the rising edge of clkin senses a logic low level on rd if cs is also low. when rd is sensed high, the output data bits, db15 to db0, are high impedance. 5 dgnd/ drdy data ready logic output. a falling ed ge indicates a new output word is availa ble to be read from the output data register. drdy returns high upon completion of a read operation. if a read operation does not occur between output updates, drdy pulses high for two clkin cycles before the next output update. drdy also indicates when conversion results are available after a sync sequence. 30 dv dd / cs chip select logic input. 31 dgnd/db15 data output bit (msb). 32 dgnd/db14 data output bit. 33 scr/db13 data output bit. 34 sldr/db12 data output bit. 35 slp/db11 data output bit. 36 tsi/db10 data output bit. 37 fso/db9 data output bit. 38 sdo/db8 data output bit. 40 sco/db7 data output bit. 41 fsi/db6 data output bit. 42 sfmt/db5 data output bit. 43 doe/db4 data output bit. 44 dgnd/db3 data output bit. ad7723 rev. c | page 13 of 32 table 8. serial mode pin function descriptions pin no. mnemonic description 1 dgnd/db2 tie to dgnd. 2 dgnd/db1 tie to dgnd. 3 dgnd/db0 tie to dgnd. 4 cfmt/ rd serial clock format logic input. the clock format pin selects whether the serial data, sdo, is valid on the rising or falling edge of the serial clock, sco. when cfmt is logic low, serial data is valid on the falling edge of the serial clock, sco. if cfmt is logic high, sdo is valid on the rising edge of sco. 5 dgnd/ drdy tie to dgnd. 30 dv dd / cs tie to dvdd. 31 dgnd/db15 tie to dgnd. 32 dgnd/db14 tie to dgnd. 33 scr/db13 serial clock rate select input. with sc r set logic low, the serial clock output frequency, sco, is equal to the clkin frequency. a logic high sets it equa l to one-half the clkin frequency. 34 sldr/db12 serial mode low/high output da ta rate select input. with sldr set logic high, the low data rate is selected. a logic low selects the high data rate. the high data rate correspon ds to data at the output of the fourth decimation filter (decimate by 16). the low data rate corre sponds to data at the output of the fift h decimation filter (decimate by 32). 35 slp/db11 serial mode low-pass/band-pass filter sele ct input. with slp set logic high, the low-pass filter response is selected. a logic low selects band-pass. 36 tsi/db10 time slot logic input. the logic level on tsi sets the active state of the doe pin. with tsi set logic high, doe enables the sdo output buffer when it is a logic high and vice versa. tsi is used when two ad7723s are connected to the same serial data bus. when th is function is not needed, tsi and doe should be tied low. 37 fso/db9 frame sync output. fso indicates the beginning of a word transmission on the sdo pin. depending on the logic level of the sfmt pin, the fso signal is either a positi ve pulse approximately one sco period wide or a frame pulse that is active low for the duration of the 16-data bit transmission. 38 sdo/db8 serial data output. the seri al data is shifted out msb first, synchr onous with the sco. serial mode 1 data transmissions last 32 sco cycles. after the lsb is output, trailing zeros are output for the remaining 16 sco cycles. serial modes 2 and 3 data tran smissions last 16 sco cycles. 40 sco/db7 serial clock output. 41 fsi/db6 frame synchronization logic input. the fs i input is used to synchronize the ad7723 serial output data register to an external source and to allow more than one ad7723, ope rated from a common master clock, to simultaneously sample its analog input and update its output register. 42 sfmt/db5 serial data format logic input. the logi c level on the sfmt pin selects the format of the fso signal for serial mode 1. a logic low makes the fso output a pulse one sco cycle wide at the beginning of a serial data transmission. with sfmt set to a logic high, the fso signal is a frame pulse th at is active low for the durati on of the 16-bit transmission. for serial modes 2 and 3, sfmt should be tied high. 43 doe/db4 data output enable logic input. the do e pin controls the three-state output buff er of the sdo pin. the active state of doe is determined by the logic level on the tsi pin. wh en the doe logic level equals the level on the tsi pin, the serial data output, sdo, is active. ot herwise, sdo is high impedance. sdo can be three-state after a serial data transmission by connecting doe to fso. in normal operations, tsi and doe should be tied low. 44 dgnd/db3 tie to dgnd. ad7723 rev. c | page 14 of 32 terminology s i g n a l -t o-n o is e r a ti o (s nr) s n r is t h e me asur e d sig n al- t o- n o is e r a t i o a t t h e o u t p ut o f t h e ad c. the sig n a l is t h e r m s ma g n i t ude o f t h e f u ndam e n t a l . n o is e is t h e r m s s u m o f al l o f t h e n o nf u ndam e n t al sig n als u p t o h a lf th e o u t p u t da ta ra t e (f o /2), excl udin g dc. th e ad c is e v a l u a te d b y a pply i ng a l o w noi s e, l o w d i stor t i o n s i ne w a ve s i g n a l to t h e i n put pi ns . by ge ne r a t i ng a f a st fou r i e r t r ans f or m (fft ) p l o t , th e s n r da ta ca n t h e n be o b ta in e d f r o m th e o u t p u t sp e c t r u m . t o t a l ha r m on i c d i s t or t i on ( t h d ) t h d i s th e ra tio o f th e rm s s u m o f th e h a rm o n i c s t o t h e rm s va l u e o f t h e f u ndam e n t a l . t h d is def i n e d as 1 2 6 2 5 2 4 2 3 2 2 v v v v v v thd + + + + = 20log w h er e v 1 is t h e r m s a m pli t ude o f t h e f u ndam e n t al, and v 2 , v 3 , v 4 , v 5 , a nd v 6 a r e t h e r m s am pl i t u d es o f t h e s e c o n d t h r o u g h s i x t h h a r m on i c s . t h e t h d i s a l s o d e r i ve d f rom t h e f f t pl ot of th e a d c o u t p u t s p ectr um . s p uri o us-f r e e d y na mi c r a n g e (s fd r) d e f i n e d as t h e dif f er en ce , in db , b e t w e e n t h e p e ak s p ur io us o r ha r m o n ic com p o n e n t i n t h e a d c o u t p u t sp e c t r um (u p t o f o /2 a nd excl udi n g dc) a n d t h e r m s v a l u e o f t h e f u nd a m e n t a l. n o r m a l ly , t h e v a l u e o f t h is sp e c if ica t ion is d e t e r m i n e d b y t h e la rg es t ha r m o n i c in t h e o u t p u t sp e c t r um o f t h e fft . f o r in p u t sig n als w h os e s e co nd ha r m onics o c c u r in t h e st o p -band r e g i on o f t h e dig i t a l f i l ter , t h e s p ur i n t h e n o is e f l o o r limi ts t h e s f d r . p a s s - band r i ppl e t h e f r e q u e nc y re sp ons e v a r i a t i o n of t h e a d 7 7 2 3 i n t h e d e f i ne d p a ss - b a n d f r e q u e nc y r a nge. p a s s - band f r e q u e nc y t h e f r eq ue n c y u p t o wh i c h t h e f r eq ue n c y r e s p o n se v a r i a t i o n is wi t h i n t h e p a ss - b a nd r i p p le sp e c if ica t ion. cuto f f f r e q u e n c y the f r eq uen c y b e lo w which t h e ad7723 s f r eq uen c y r e s p o n s e w i l l not h a ve m ore t h an 3 d b of a t t e n u a t i on . sto p - b a n d fr e q u e n c y the f r eq uen c y abo v e which t h e ad7723 s f r eq uen c y r e s p o n s e w i ll be wi th in i t s s t o p - b a n d a t t e n u a t i o n. sto p - b a n d a t te nu at i o n the ad7723 s f r eq uen c y r e s p o n s e wil l n o t ha ve les s tha n 90 db o f at t e nu at i o n i n t h e s t at e d f r e q u e n c y b a n d . inte g r a l n o n l i n e a r i t y this is t h e maxi m u m de v i a t io n o f a n y co de f r o m a st raig h t li n e pa s s i n g th r o ug h th e en d p o i n t s o f th e tra n s f e r fun c ti o n . th e end p o i n t s o f t h e t r a n sfer f u n c t i o n a r e mi n u s f u l l s c ale , a p o i n t 0.5 ls b b e lo w t h e f i rs t c o de tran si tio n (100 . . . 00 t o 100 . . . 01 in b i p ola r mo de, 000 . . . 00 t o 000 . . . 01 in uni p ola r mo de), a nd pl us f u l l s c a l e , a p o i n t 0.5 l s b a b o v e t h e last co de t r a n s i t i on (011 . . . 10 t o 011 . . . 11 in b i p o la r m o de , 111 . . . 10 t o 111 . . . 11 in uni p ola r m o de). th e er r o r is exp r es s e d i n ls bs. d i f f erenti a l n o n l i n e a r i ty this is t h e dif f er en ce b e tw e e n t h e m e as ur e d and t h e i d e a l 1 lsb cha n g e b e t w e e n tw o ad jace n t co des in t h e ad c. c o m m o n- m o d e rej e c t i o n r a t i o the a b i l i t y o f a de vice t o r e je c t t h e ef fe c t o f a v o l t a g e a p plie d to bo t h in p u t t e rmi n als si m u l t a n e o us l y o ft e n thr o u gh v a ria t i o n of a g rou nd l e ve l i s sp e c i f i e d a s a c o m m on C m o d e re j e c t i o n ra ti o . c m rr i s th e ra ti o o f g a i n f o r th e d i f f e r e n ti al s i g n al t o t h e ga in fo r t h e comm on- m o d e si g n al. un i p o l a r o f f s e t e r r o r u n i p ola r o f fs et er r o r is t h e de v i a t io n o f t h e f i rst co de t r a n si t i o n (10 . . . 000 t o 10 . . . 001) f r o m th e ide a l dif f er e n t i al v o l t a g e (vin (+) C vin(C)+ 0.5 ls b) wh en o p era t in g in t h e uni p o l a r mo d e . b i p o l a r off s et err o r this is t h e de via t io n o f t h e mids cale tra n s i tion co de (111 . . . 11 t o 000 . . . 00) f r o m t h e ideal dif f er en tial v o l t a g e (vin(+) C vin(C) C 0.5 ls b) wh e n o p er a t in g in t h e b i p o lar m o de . ga in e r r o r the f i rs t co de t r a n si t i on sh o u ld o c c u r a t an a n al og val u e ? lsb ab o v e C f u l l s c a l e. t h e l a st t r ans i t i on s h ou l d o c c u r for an an a l o g val u e 1 ? ls b b e lo w t h e n o minal f u l l s c ale . ga i n er r o r is t h e de v i a t io n o f t h e ac t u a l d i f f er en c e b e tw e e n f i rst a nd last co d e t r a n si t i o n s and t h e ide a l d i f f er en ce b e tw e e n f i r s t an d last c o de tra n s i ti o n s . ad7723 rev. c | page 15 of 32 typical perf orm ance cha r acte ristics av dd = d v dd = 5 v ; t a = 25c; clki n = 19.2 mh z; exter nal 2.5 v r e f e r e n c e , unles s o t h e r w is e n o t e d . analog input level (db) 110 40 ?50 ? 40 (db) ?3 0 ? 2 0 ?1 0 0 100 90 80 60 50 70 thd signal frequency = 98khz measurement bandwidth = 460khz sfdr snr 01186-012 f i gure 12. snr, t h d , and sf dr v s . a n al og input l e ve l re lative to f u ll s c a l e ( o utput da ta r a t e = 1 . 2 m h z) analog input level (db) 110 40 ?50 0 ?40 (db) ?30 ? 20 ?1 0 100 90 80 60 50 70 thd signal frequency = 98khz measurement bandwidth = 300khz sfdr snr 01186-013 f i gure 13. snr, t h d , and sf dr v s . a n al og input l e ve l re lative to f u ll s c a l e ( o utput da ta r a t e = 600 khz) 102 100 84 (db) 92 90 88 86 96 94 98 temperature (c) 100 ?2 5 0 2 5 5 0 7 5 ?5 0 signal frequency = 98khz measurement bandwidth = 460khz snr thd 3rd 2nd 01186-014 f i g u re 14. snr and thd v s . t e mper at u r e (o ut put d a t a r a te = 1. 2 m h z) 106 104 88 (db) 96 94 92 90 100 98 102 temperature ( c) 100 ? 2 5 0 25 50 75 ?5 0 snr thd 2nd 3rd signal frequency = 98khz measurement bandwidth = 300khz 01186-015 f i gure 15. snr and thd v s . t e mper atu r e (o utput d a t a ra te = 6 0 0 kh z) output word rate (khz) 106 92 100 500 (db) 1000 1500 2150 104 102 100 96 94 98 snr thd sfdr 90 88 86 84 input signal = 10khz measurement bandwidth = 0.383 owr 01186-016 f i gure 16. snr, t h d , and sf dr v s . s a mpl i ng f r equ e nc y ( d e c i m a t e by 1 6 ) output word rate (khz) 115 90 50 150 (db) 300 600 900 110 105 95 100 snr thd sfdr input signal = 10khz measurement bandwidth = 0.5 owr 450 750 01186-017 f i gure 17. snr, t h d , and sf dr v s . s a mpl i ng f r equ e nc y ( d e c i m a t e by 3 2 ) ad7723 rev. c | page 16 of 32 code 2000 0 32700 32713 32702 fre q ue ncy of occurre nce 32704 32706 32708 32710 32712 1800 800 600 400 200 1400 1000 1600 1200 v in (+) = v in (? ) 8192 samples taken 01186-018 f i gure 1 8 . hi st o g r a m o f o u tput c o des wi th dc input ( o utput da ta r a t e = 1 . 2 m h z) code 5000 0 32703 32710 32704 fre q ue ncy of occurre nce 32705 32706 32707 32708 32709 4500 2000 1500 1000 500 3500 2500 4000 3000 v in (+) = v in (? ) 8192 samples taken 01186-019 f i gure 1 9 . hi st o g r a m o f o u tput c o des wi th dc input ( o utput da ta r a t e = 600 khz) 1.0 0.8 ? 0.8 0 65535 16384 32768 49152 0.2 ? 0.2 ? 0.4 ? 0.6 0.6 0.4 0 ? 1.0 67108864 samples taken differential mode code dnl e rror (ls b ) 01186-020 f i gure 20. d i ffe r e n t ial no nl ine a r i t y (o utput d a t a rate = 1.2 mh z) ad8047 ad8047 r fb 220 ? 220 ? 27 ? 220pf a1 a2 vin(+) vin( ?) ref1 ref2 ad7723 10nf 220nf 220 ? 27 ? ain = 2v biased about ground 1 f r source 50 ? r in 390 ? r balance1 22 0 ? g ain = 2 r fb /(r in + r source ) r balance1 = r balance2 (r in + r source )/(2 r fb ) r ref2 = r ref1 (r in + r source )/r fb r ref1 10k ? r ref2 20k ? r balance2 r balance2 01186- 021 21 23 19 20 f i g u re 21. d i f f e r e nt ia l n o nl in ea rit y (o ut put d a t a r a te = 60 0 k h z) 1.0 0.8 ?0.8 0 65535 16384 32768 49152 0.2 ?0.2 ?0.4 ?0.6 0.6 0.4 0 ?1.0 67108864 samples taken differential mode code inl e rror (ls b ) 01186-022 f i gure 22. integ r a l non lin ea rit y (o utp u t d a t a rate = 1 .2 mh z) 1.0 0.8 ?0.8 0 65535 16384 32768 49152 0.2 ?0.2 ?0.4 ?0.6 0.6 0.4 0 ?1.0 67108864 samples taken differential mode code inl erro r (lsb) 01186-023 f i g u re 23. integ r a l non lin ea rit y (o ut p u t d a t a r a te = 6 00 k h z) ad7723 rev. c | page 17 of 32 clock frequency (mhz) 225 150 0 02 5 0 ? 120 0 300k 50k 100k 150k 200k 250k ?20 ?40 ?60 ?80 ? 100 snr = ? 89.91db snr + d = ? 89.7db thd = ? 101.16db sfdr = ? 102.1db 2nd harmonic = ? 102.1db 3rd harmonic = ? 110.3db a in = 50khz measured bw = 300khz ? 140 ? 160 power level relative to full scale (db) frequency (hz) 01186-026 p o we r (mw) 51 0 1 5 2 0 200 175 125 100 ai dd (half_power = 1) di dd ai dd (half_power = 0) 75 50 25 01186-024 f i gure 24. p o wer consumpt ion vs. clkin f r eq uenc y 0 ?150 0 600k 100k 200k 300k 400k 500k ?25 ?50 ?75 ?100 ?125 snr = ? 86.19db snr + d = ? 85.9db thd = ? 96.42db sfdr = ? 99.61db 2nd harmonic = ? 100.98db 3rd harmonic = ? 99.61db a in = 100khz measured bw = 460khz pow e r level r e la tive to fu ll sc a l e ( d b ) frequency (hz) 01186-025 f i g u re 25. 1 6 k p o i n t fft (o ut put d a t a r a te = 1. 2 m h z) f i g u re 26. 1 6 k p o i n t fft (o ut put d a t a r a te = 60 0 k h z) ad7723 rev. c | page 18 of 32 circuit description the ad7723 ad c em p l o y s a - con v ersio n tec h niq u e t o co n v er t t h e a n alog in p u t in t o a n e q ui vale n t dig i t a l w o r d . th e m o d u l a t o r s a m p les t h e in pu t w a v e fo r m a nd o u t p u t s a n eq ui v a len t d i g i t a l w o r d a t th e in p u t c l oc k f r eq uen c y , f clkin . due t o th e h i gh o v e r sa m p lin g ra t e tha t s p r e a d s th e q u a n tiz a ti o n noi s e f rom 0 to f clkin /2, t h e n o is e en erg y co n t ai n e d i n t h e b a nd of i n te re st i s re du c e d ( f i g u r e 2 7 a ) . t o f u r t he r re d u c e t h e q u a n tiz a ti o n n o i s e , a hi g h - o r d er m o d u la t o r i s e m p l o y ed t o s h a p e t h e n o is e s p e c t r um s o t h a t m o s t o f t h e n o is e e n erg y is sh i f te d out of t h e b a n d of i n te re st ( f i g u r e 2 7 b ) . t h e di gi t a l f i l t er th a t f o llo w s th e m o d u la t o r r e m o v e s th e la r g e out - of - b a n d q u an t i z a t i on noi s e ( f i g u r e 2 7 c ) w h i l e a l s o r e d u cin g t h e da t a ra te f r o m f clkin a t t h e in p u t o f t h e f i l ter t o f clkin /32 o r f clkin /16 a t t h e o u t p u t o f t h e f i lt er , dep e n d in g on t h e s t a te o n t h e mod e 1/mo d e 2 p i n s i n p a ral l e l i n t e r f ace m o de o r th e s l d r p i n in s e r i al in t e r f ace m o de . the ad7 723 o u t p u t da t a ra t e is a l i t t le o v er tw ice t h e sig n al b a n d wi d t h, w h ich gua r an t e es tha t t h er e is n o l o s s o f da t a in t h e sig n al band . dig i t a l f i l t er in g has cer t a i n ad van t a g es o v er a n al og f i l t er in g. f i rs t, si nce dig i t a l f i l t er in g o c c u rs a f t e r t h e a/d co n v ersio n , i t ca n r e m o v e n o i s e i n je c t e d d u r i n g t h e con v ersi o n p r o c es s. ana l og f i l t er in g ca n n o t r e m o v e n o is e in j e c t e d d u r i n g co n v ersio n . s e c o n d , t h e dig i t a l f i l t er co m b i n es l o w p a s s -b and r i p p le w i t h a st e e p r o l l -o f f w h i l e a l s o ma in t a in ing a li n e a r phas e re sp ons e . noise shaping quantization noise digital filter cutoff frequency f clkin /2 band of interest band of interest band of interest a b c 01186-027 f clkin /2 f clkin /2 f i gur e 2 7 . si g m a-d e l t a adc the ad7723 em p l o y s f o ur o r f i v e f i ni t e im p u ls e r e s p o n s e (fir) f i l t er s in s e r i es. e a c h individ u al f i l t er s o u t p u t da ta ra t e is half t h a t o f th e fi l t e r s i n p u t d a ta r a t e . w h e n d a ta i s f e d t o th e i n t e rfa c e f r o m t h e o u t p u t o f th e f o ur th f i l t e r , th e o u t p u t d a ta ra t e is f clkin /16 a nd t h e r e s u l t i n g o v ers a m p li n g ra t i o (os r ) o f t h e co n v er t e r is 16. d a t a fe d t o t h e in t e r f ace f r o m t h e o u t p ut o f t h e f i f t h f i l t er r e s u l t s i n a n o u t p u t da t a ra te o f f clkin /32 an d a co r r es p o n d in g os r fo r t h e con v er t e r o f 32. w h e n a n o u t p ut da ta ra t e (o d r ) o f f clkin / 3 2 i s se l e ct e d , th e d i g i ta l fi l t e r r e s p o n s e ca n b e s et t o e i t h er lo w-p a s s o r b a n d - p as s. th e b a nd- p a s s r e s p o n s e is us ef u l w h e n t h e in pu t sig n al is b a nd li mi t e d b e c a us e t h e r e s u l t in g o u t p u t da t a ra te is half t h a t r e q u ir e d t o co n v er t t h e b a nd w h e n t h e lo w- p a s s o p era t i n g m o de is us e d . t o ill u s t ra t e t h e o p e r a t i o n o f th i s m o d e , co n s id e r a ba n d - l im i t e d sig n al , as sh o w n in f i gur e 28a. this sig n al b a nd can b e co rr ectl y co n v e r t e d b y s e lectin g th e (lo w - p a s s ) o d r = f clkin /16 mo de, as sho w n in f i gure 2 8 b . n o te t h a t t h e ou t p u t da t a r a te is a li t t le o v e r twice t h e ma xim u m f r e q uen c y in t h e f r eq uen c y b a n d . al ter na t i vely , t h e b a nd-p a ss m o de can b e s e le c t e d , as sh o w n i n f i gur e 28c. the ba nd-p a s s f i l ter r e m o v e s u n wan t e d sig n als f rom d c to ju st b e l o w f clkin / 6 4 . r a th e r t h a n o u t p u t ti n g d a t a a t f clkin /16, t h e o u t p u t o f t h e b a n d -p as s f i l t er is s a m p le d a t f clkin / 32. t h i s ef f e cti v e l y tra n s l a t e s t h e w a n t ed ba n d t o a maxim u m f r eq uen c y o f a li t t le les s tha n f clkin /64, as s h o w n in f i gur e 28d . h a lvin g t h e o u t p u t da t a ra t e r e d u ce s t h e w o rklo ad o f a n y f o llo w i n g si gn al p r oces so r a n d also allo ws a lo w e r ser i al cl o c k r a te to b e u s e d . band limited signal 0db 0db odr low-pass filter response sample image low-pass filter. output data rate = f clkin /16 0db sample image band-pass filter response band-pass filter f clkin /16 low-pass filter. output data rate = f clkin /32 odr sample image frequency translated input signal 0db a b c d 01186-028 f clkin /16 f clkin /16 f clkin /16 f i gure 28. band-p ass o p er ation t h e f r e q u e nc y re sp ons e of t h e t h re e d i g i t a l f i lte r op e r a t i n g m o des is sh o w n in f i gur e 29, f i gur e 30, a nd f i g u r e 31. ad7723 rev. c | page 19 of 32 f i g u re 3 2 s h o w s t h e f r e q u e nc y re sp ons e of t h e d i g i t a l f i lte r i n b o t h lo w - p a ss and b a n d -p ass mo des. d u e to t h e s a m p li n g n a tu re of t h e c o n v e r te r , t h e p a ss - b a n d re s p ons e i s re p e a t e d a b o u t t h e i n p u t s a m p ling f r e q uen c y , f clkin , an d a t in t e g e r mu l t i p l e s o f f clk i n . o u t-o f - b an d n o is e o r sig n als co in c i de n t wi t h a n y o f t h e f i l t er ima g es a r e a l ias e d do w n t o t h e p a s s b a nd . h o w e v e r , d u e to th e ad7723 s hig h o v ers a m p l i n g ra tio , t h es e ba n d s o c c u p y onl y a smal l f r ac t i o n o f t h e s p e c t r um, a nd m o s t b r o a d b a n d n o i s e i s at t e n u at e d b y at l e a s t 9 0 d b . in a d d i t i o n , a s s h o w n i n f i gur e 33, wi t h e v en a lo w-o r d er f i l t er , t h er e is sig n if ican t a t ten ua t i on a t t h e f i rs t ima g e f r e q uen c y . this co n t ras t s w i t h a n o r m al n y q u ist ra t e con v er t e r w h er e a v e r y h i g h - ord e r an t i a l i a s f i lt e r i s re qu i r e d to a l l o w mo st of t h e b a ndwi d t h t o b e us e d w h i l e ens u r i n g s u f f i cien t a t t e n u a t io n a t mu l t i p l e s o f f clk i n . f clkin 0 1.0 0.5 0db ?100db 01186-029 f i g u re 29. l o w- p a s s f ilt er d e c i m a te by 16 0 1.0 0.5 0db ? 100db 01186-030 f clkin f i g u re 30. l o w- p a s s f ilt er d e c i m a te by 32 0 1.0 0.5 0db ?100db 01186-031 f clkin f i g u re 31. ba nd-p a s s f ilt er d e ci m a te by 32 1 f clkin 2 f clkin 3 f clkin 0db 01186-032 fi g u r e 3 2 . d i g i t a l fi l t e r f r e q u e n c y r e s p o n s e f clkin /32 0db f clkin required attenuation antialias filter response output data rate 01186-033 f i g u re 33. f r equen c y r e s p ons e of a n t i al ias f i l t er ad7723 rev. c | page 20 of 32 applying the ad7723 analog input range the ad7723 has dif f er en tial in p u ts t o p r o v ide co mm on-m o d e n o is e r e je c t ion. i n uni p ol a r m o de , t h e a n alog i n p u t ra n g e is 0 to 8/5 v ref2 , w h i l e in b i p o la r mo de , t h e a n alog i n p u t ra n g e is 4/5 v ref2 . th e o u t p u t co de is tw os co m p lemen t b i na r y in bo t h m o d e s wi t h 1 l s b = 61 v . t h e i d eal in p u t / o u t p u t tra n s f er cha r ac t e r i s t ics fo r t h e tw o m o des a r e s h o w n i n f i gur e 34. i n bo t h m o d e s , th e a b so l u t e v o l t a g e o n ea ch in p u t m u s t r e m a in wi t h i n t h e s u p p ly ra n g e a g nd t o a v dd . th e b i p o la r mo de al lo ws ei t h er sing le-en d e d o r co m p lem e n t a r y in p u t sig n als. 011? 111 011? 110 000? 010 000? 001 000? 000 111? 111 111? 110 100? 000 100? 001 ? 4/5 v ref2 0v +4/5 v ref2 ? 1lsb bipolar (0v) (+4/5 v ref2 ) (+8/5 v ref2 ? 1lsb) unipolar 01186- 034 f i gure 34. bipolar ( u nip o lar) mod e t r ansfer f u n c tion the ad7723 ac cep t s f u l l -s cale , in-ban d sig n als. h o w e v e r , la rg e s c ale o u t-o f -b and sig n als can o v erlo ad t h e m o d u la t o r i n p u t s . fi g u r e 3 5 s h ow s t h e m a x i m u m i n put s i g n a l l e v e l a s a f u n c t i o n o f f r e q uen c y . a mini mal si n g le- p ole , r c , a n t i al i a s f i l t er s et t o f clkin /24 al lo ws f u l l -s cale in pu t sig n als o v er t h e en t i r e f r e q ue n c y s p ectr um . input signal frequency relative to f clkin 0 0.5 0.02 0.04 0.06 0.08 0.10 0.12 0.14 2.2 2.1 1.3 peak input (v p-p) 1.7 1.6 1.5 1.4 1.9 1.8 2.0 v ref = 2.5v 01186-035 f i gure 3 5 . p e a k inp u t si gnal l e v e l vs . si gnal f r equ e nc y analog input the a n alog i n pu t o f t h e ad772 3 us es a sw i t ch e d ca p a c i t o r t e chni q u e t o s a m p le t h e i n p u t sig n al. f o r t h e pur p os e o f dr i v i n g th e ad7723, an eq ui valen t c i r c ui t o f t h e a n alo g in p u ts is sh o w n in f i gur e 36. f o r eac h half c l o c k c y c l e , tw o hig h l y linea r sa m p li n g ca pa ci t o r s a r e s w i t ch e d t o bo th i n p u t s , co n v e r ti n g th e i n p u t s i gn al i n t o a n eq u i val e n t sa m p l e d c h a r g e . a s i gn al so u r c e dr i v in g t h e a n a l og in p u ts m u st b e ab le t o s o ur c e t h is cha r ge while als o s e t t lin g t o t h e r e q u ir ed acc u rac y b y t h e end o f eac h half-c lo c k p h as e . 500 ? 500 ? ad7723 clkin vin(+) vin(?) ac ground 2pf 2pf a b a b a b a b 20 19 01186-036 f i gure 36. a n a l og i n put equiv a l e nt c i rcuit driving th e analog inputs t o in t e r f ace t h e sig n al s o ur ce t o th e ad7723, a t leas t on e o p am p i s ge ne r a l l y re qu i r e d . c h oi c e of op am p i s c r it i c a l to ac hie v in g t h e f u l l p e r f o r ma n c e o f th e ad7723. the o p a m p n o t o n ly has t o r e co v e r f r o m t h e t r an sien t lo ads t h a t t h e ad c i m p o s e s on it , but it m u st a l s o h a ve go o d d i s t or t i on cha r ac t e r i st ics and v e r y lo w in pu t n o i s e . resist ors in t h e sig n a l p a t h can als o add t o t h e o v eral l t h er ma l n o i s e f l o o r , ne c e ss it a t i n g t h e choi c e of l o w v a lu e re s i stor s . p l aci n g an r c f i l t er b e tw e e n t h e dr i v e s o ur ce and t h e a d c in p u ts, as sho w n in f i gur e 37, has a n u m b er o f ben e f i c i al ef fe c t s. t r a n sien ts o n t h e o p am p o u t p u t s a r e si g n if ica n t l y r e d u ce d b e c a us e t h e ext e r n al c a p a ci t o r n o w s u pplies t h e in s t an t a n e o u s cha r g e r e q u ir e d w h en t h e s a m p l i n g c a p a ci t o rs a r e swi t ch e d t o t h e ad c i n p u t p i n s a nd i n p u t c i r c ui t n o is e a t t h e s a m p le ima g es i s n o w sig n if i c a n t l y a t t e n u a t e d , resu l t in g in im p r o v e d o v era l l s n r . th e ext e r n al r e sis t o r s e r v es t o is ola te t h e ext e r n al ca p a c i to r f r o m t h e ad c o u t p ut, t h us i m p r o v in g o p am p st a b i l it y w h i l e a l s o i s o l at i n g t h e op a m p output f rom a n y r e ma ini n g t r a n s i en ts on t h e ca p a ci t o r . b y exp e r i m e n t i n g wi t h dif f er en t f i l t er v a l u es, t h e o p t i m u m p e r f o r ma n c e ca n b e a c h i ev e d f o r ea c h a p p l ica t i o n . a s a g u i d e l in e , t h e r c tim e co n s ta n t (r c) s h o u ld b e le s s th a n a q u a r t e r o f th e c l ock p e r i o d t o a v o i d n o nl i n e a r c u r r en ts f r o m t h e a d c in p u ts b e ing sto r e d o n t h e ex ter n a l c a p a ci to r a nd deg r a d i n g disto r t i o n . this r e st r i c t io n m e an s t h a t t h is f i l t e r ca nn ot fo r m t h e main an t i a l ia s f i l t er fo r t h e ad c. ad7723 rev. c | page 21 of 32 vin(+) vin(? ) ad7723 r r c 01186-037 f i g u re 37. input r c net w ork w i th th e un i p o l a r i n p u t m o d e se l e ct ed , j u s t o n e o p a m p i s r e q u ir e d to b u f f er sin g le-e nde d in p u t sig n a l s. h o w e ver , dr i v in g th e ad7723 wi t h co m p lem e n t ar y sig n als a n d wi th t h e b i p o la r in p u t ra n g e s e le c t e d has s o me dis t i n c t ad van t a g es: e v en-o r d er ha r m o n ics in b o th t h e dr i v e circ ui ts and t h e ad7723 f r o n t end a r e a t t e n u a t e d and t h e p e ak-t o- p e ak in p u t sig n al ra n g e o n b o t h in p u ts is halv e d . h a lv in g t h e i n pu t sig n al ra n g e al lo ws s o m e o p a m ps t o b e p o wer e d f r o m th e s a m e s u p p lies as th e ad7723. al t h o u g h a co m p lem e n t a r y dr i v er r e q u ir es t h e us e o f tw o o p a m ps p e r ad c, i t ma y a v o i d t h e n e e d t o g e n e r a t e addi tio n al s u p p lies j u s t fo r t h es e o p a m ps. f i gur e 38 an d f i gur e 39 sh o w tw o s u c h cir c ui ts f o r dr i v in g t h e ad7723. f i gur e 38 is in t e nded fo r us e wh en t h e in p u t sig n al is b i as e d ab o u t 2.5 v , w h i l e f i gur e 39 is us e d w h e n t h e in p u t s i g n a l is b i as e d ab out g r o u nd. w h i l e b o t h c i r c u i ts c o n v e r t t h e i n put sig n a l in t o a com p l e me n t a r y s i g n a l , t h e c i rc u i t in f i gure 3 9 al s o l e v e l s h if ts t h e si g n al s o t h a t b o t h o u t p u t s a r e b i as e d ab o u t 2.5 v . s u i t a b le o p am p s in cl ude t h e ad8047, ad8044 , ad8041, an d i t s d u al e q ui valen t , t h e ad8042. the ad8047 has lo w e r in p u t n o is e tha n the ad8041/ad80 42 b u t has t o be s u p p lied f r o m a +7.5 v/?2.5 v su p p l y . th e ad8 041/ad8042 ty p i cal l y deg r ades sn r f rom 9 0 d b to 8 8 d b but c a n b e p o w e re d f rom t h e s a me sin g le 5 v su p p ly as th e ad772 3. ad8047 ad8047 r fb 220 ? 220 ? 27 ? 220pf a1 a2 vin(+) vin(? ) ref1 ref2 ad7723 10nf 220nf 220 ? 27 ? ain = 2v biased about 2.5v 1 f r source 50 ? r in 390 ? gain = 2 r fb /(r source + r in ) 10k ? 01186-038 21 23 19 20 f i gure 38. sing le -ended-to - d i fferent ia l input cir c ui t for bi p o la r m o de o p er at ion (a na log input bi as ed a b o u t 2. 5 v ) ad8047 ad8047 r fb 220 ? 220 ? 27 ? 220pf a1 a2 vin(+) vin(?) ref1 ref2 ad7723 10nf 220nf 220 ? 27 ? ain = 2v biased about ground 1 f r source 50 ? r in 390 ? r balance1 220 ? g ain = 2 r fb /(r in + r source ) r balance1 = r balance2 (r in + r source )/(2 r fb ) r ref2 = r ref1 (r in + r source )/r fb r ref1 10k ? r ref2 20k ? r balance2 r balance2 01186- 039 21 23 19 20 f i gure 39. sing le -ended-to - d i fferent ia l input cir c ui t for bi p o la r m o de o p er at ion (a na log input bi as ed a b o u t ground) applying the reference the r e f e r e n c e c i r c ui tr y us ed in t h e ad7723 in c l udes a n o n -c hi p 2 . 5 v b a nd - g a p re f e re nc e a n d a re f e re nc e bu f f e r c i rc u i t . t h e bl o c k d i ag r a m o f t h e re f e re nc e c i rc u i t i s s h ow n i n f i g u re 4 0 . the i n t e r n al r e fer e n c e v o l t a g e i s co nn e c t e d t o ref1 t h r o ug h a 3 k? r e sis t o r a nd is in t e r n al l y b u f f er ed t o dr i v e th e analog m o d u l a t o r s s w i t c h e d c a p d a c (ref2). w h e n usin g t h e i n te r n a l re fe re nc e, a 1 f c a p a c i tor i s re qu i r e d b e t w e e n r e f 1 a nd a g n d to d e co u p le t h e b a nd-ga p n o is e. i f t h e in ter n a l r e fer e n c e is r e quir e d t o b i as ex ter nal cir c ui ts, u s e a n exter nal p r e c isio n o p a m p t o b u f f er ref1. comparator reference buffer 1v 1 f ref2 ref1 2.5v reference switched-cap dac referenced ad7723 3k ? 01186-040 23 21 f i gure 40. r e ference ci r c u i t b l o c k d i ag r a m w h er e ga i n er r o r o r ga in er r o r dr if t r e q u ir es t h e us e o f a n e x te r n a l re f e re n c e, t h e re f e re nc e bu f f e r i n f i g u r e 4 0 c a n b e t u r n e d o f f b y g r o u ndin g t h e re f 1 p i n an d t h e e x ter n a l r e f e r e n c e can b e a p p l ie d dir e c t ly t o ref2 p i n. the ad7723 accep t s an ext e r n al r e f e r e n c e v o l t a g e betw een 1. 2 v t o 3.15 v . b y a p p l yin g a 3 v ra t h er tha n a 2.5 v r e f e r e n c e , s n r is typ i c a l l y im p r o v e d b y a b o u t 1 db . w h ere t h e o u t p u t comm on- m o d e ra n g e o f t h e am plif ier dr i v in g t h e in pu ts is r e st r i c t e d , t h e f u l l - s c ale in p u t sig n al s p a n c a n be r e d u ced b y a p p l y i n g a lo w e r tha n 2.5 v r e f e r e n c e . f o r exa m p l e , a 1.25 v r e f e r e n c e w o u l d make t h e b i p o la r i n p u t s p a n 1 v b u t w o u l d deg r ade s n r . ad7723 rev. c | page 22 of 32 1m ? xtal clkin ad7723 01186-043 i n all ca se s , s i n c e th e r e f2 v o l t a g e co nn ects t o th e a n alog m o d u l a to r , a 22 0 nf a nd 10 nf ca p a ci to r m u st co nn e c t d i r e c t ly f r o m ref2 t o a g nd . the ext e r n al ca p a c i t o r p r o v i d es t h e cha r g e r e q u ir e d fo r t h e d y na mi c lo ad p r es en t e d a t t h e ref2 p i n (s ee f i gur e 41). 10nf 220nf a b b a 4pf 4pf ref2 switched-cap dac referenced clkin a b a b ? 01186-041 23 f i gure 43. cr ystal o s cillator c o nnec t ion w h e n a n e x t e rnal c l oc k so ur ce is be in g use d , t h e i n t e rn al os cil l a t o r cir c u i t ca n be dis a b l e d b y tyin g xt al_o ff hig h . a lo w phas e n o is e clo c k sh o u ld b e us e d t o g e nera te t h e ad c s a m p ling clo c k b e c a us e s a m p li n g clo c k ji t t er ef fe c t i v e l y m o d u l a t e s t h e i n p u t sig n al an d ra is es t h e n o i s e f l o o r . th e s a m p ling c l o c k g e n e ra t o r sh o u ld b e is ol a t e d f r o m n o isy dig i tal c i rc u i t s , g rou nd e d , a n d he av i l y d e c o upl e d to t h e an a l o g g rou nd pl ane. f i gure 41. r e f2 eq uiv a l e nt input c i rc uit the ad780 is ideal t o us e as an ext e r n al r e f e r e n c e wi t h t h e ad7723. f i gur e 42 s h o w s a s u g g es t e d co nn ec tio n dia g ra m. g r o u n d in g p i n 8 o n the ad780 s e lec t s the 3 v o u t p u t m o de. t h e s a m p l i ng cl o c k ge ne r a tor s h ou l d b e re f e re nc e d to t h e an a l o g g rou nd i n a spl i t g rou nd s y ste m . h o we v e r , t h i s i s no t al wa ys p o s s i b le bec a us e o f sys t em co n s train t s. i n man y ap p l i c at i o n s , t h e s a mp l i n g c l o c k mu s t b e d e r i v e d f r o m a h i g h e r f r eq uen c y m u l t i p ur p o s e sys t em c l o c k tha t is g e nera t e d on t h e dig i tal g r o u n d plan e . i f t h e c l o c k sig n al is p a s s e d b e tw een i t s o r ig in o n a dig i t a l g r o u n d plan e t o th e ad7723 o n t h e a n alog g r o u n d plan e , t h e g r o u n d n o is e b e tw e e n t h e two pla n es adds dir e c t ly t o t h e cl o c k an d p r o d uc es exces s ji t t er . the ji t t e r can ca us e deg r a d a t i o n in t h e sig n a l -to - n o is e r a t i o and a l s o p r o d uce un w a n t e d ha r m o n ics. this ca n b e r e m e die d s o me w h a t b y tra n s m i t ti n g t h e sa m p li n g si gn al a s a d i f f e r e n t i al o n e , us i n g ei t h er a smal l r f t r a n sfo r m e r o r a hig h s p e e d dif f er en t i al dr i v e r a nd a r e cei v er such as p e cl. i n ei t h er cas e , t h e o r ig inal mast er sys t em clo c k sho u ld b e g e n e r a te d f r o m a lo w phas e n o is e cr ys t a l oscilla t o r . 1 2 3 4 ad780 ad7723 ref2 ref1 5v 1 f 22nf 220nf 10nf 22 f nc +v in temp gnd o/p select nc v out trim 2.5v nc = no connect 8 7 6 5 01186-042 f i gure 42. e x ter n a l r e fer e n c e c i rcuit conne c t io n clock generation the ad7723 con t a i n s a n os cil l a t o r cir c ui t t o al l o w a cr ys tal o r a n ext e r n al clo c k sig n al t o g e n e ra t e t h e mas t er clo c k fo r t h e a d c . th e co nn ecti o n dia g ra m f o r use w i th a cr ys tal i s s h o w n in f i gur e 43. c o n s u l t t h e ma n u f a c t ur er s r e co mm e n da t i o n fo r t h e lo ad ca p a c i to rs. t o ena b le t h e os ci l l a t o r cir c ui t o n b o a r d t h e ad7723, xt al _o ff s h o u ld be tied lo w . ad7723 rev. c | page 23 of 32 system synchronization the sync input provides a synchronization function for use in parallel or serial mode. sync allows the user to begin gathering samples of the analog input from a known point in time. this allows a system using multiple ad7723s, operated from a common master clock, to be synchronized so that each adc simultaneously updates its output register. in a system using multiple ad7723s, a common signal to their sync inputs synchronizes their operation. on the rising edge of sync, the digital filter sequencer is reset to 0. the filter is held in a reset state until a rising edge on clkin senses sync low. a sync pulse, one clkin cycle long, can be applied synchronous to the falling edge of clkin. this way, on the next rising edge of clkin, sync is sensed low, the filter is taken out of its reset state, and multiple parts begin to gather input samples. following a sync, the modulator and filter need time to settle before data can be read from the ad7723. drdy goes high following a synchronization and it remains high until valid data is available at the interface. when operating in any of the serial modes, either sync or frame sync input (fsi) may be used to synchronize multiple ad7723 devices to a common master clock. the functionality of fsi is detailed in the serial interface section. ad7723 rev. c | page 24 of 32 data interfacing the ad7723 o f f e rs a c h o i ce o f s e r i al o r p a ral l e l da ta in t e r f ace o p ti o n s t o m eet th e r e q u i r em en ts o f a v a ri et y o f s y s t e m co nf igura t io n s . i n p a ral l e l m o de , m u l t i p le ad7 723s ca n easil y be co nf igur e d to s h a r e a co mmo n da t a b u s. s e r i al m o de is idea l w h en i t is r e q u i r e d t o minimize t h e n u m b er o f da t a in t e r f ace lin e s co nn ec t e d t o a h o st p r o c ess o r . i n ei t h er cas e , ca r e f u l a t t e n t io n t o t h e syst em co nf igur a t io n is r e q u ir e d t o r e a l i z e t h e hig h d y namic ra n g e a v a i l a b l e wi th t h e ad7723. c o n s u l t the r e co mm e n d a t i on s in t h e gr o u ndin g and l a yo ut s e c t ion. t h e fol l o w in g r e co mmend a t ion s fo r p a ra l l e l in t e r f acin g a l s o a p ply f o r th e s y s t e m de s i gn w h en us i n g th e se rial m o de . parallel interf ace w h en usin g t h e ad7723, p l ac e a b u f f er/la t c h ad jacen t t o t h e co n v er t e r t o is ol a t e t h e co n v er t e r s da t a l i n e s f r o m an y n o is e tha t ma y b e o n th e da t a b u s. e v en t h o u g h t h e ad7723 has three s t a te o u t p u t s, us e o f a n is ola t io n la t c h r e p r es e n ts g o o d desig n pr a c t i c e . f i gur e 44 sh o w s h o w t h e p a ral l el in t e r f ace o f t h e ad7723 can b e co nf igur e d to in t e r f ac e wi t h t h e sys tem da t a b u s o f a m i c ropro c e ss or or a m i c r o c on t r o l l e r , su ch a s t h e mc 6 8 h c 1 6 o r 8x c251. w i t h cs a nd rd ti ed pe rm a n en tl y lo w , t h e da ta o u t p u t b i t s a r e alw a ys ac t i v e . w h en dr d y g o es hig h fo r tw o clo c k c y cles, t h e r i sin g e d g e o f dr d y is us ed t o l a t c h t h e co n v er sio n da ta be f o r e a n e w co n v e r s i o n r e s u l t i s loa d ed i n t o th e o u t p u t da t a r e g i s t er . the fal l in g e d g e o f dr d y th en sen d s a n a ppropr i a t e i n te r r upt s i g n a l for i n te r f ac e c o n t rol. a l te r n a t iv ely , if b u f f ers a r e us e d ins t e a d o f l a tch e s, t h e fal l i n g e d g e o f dr d y p r o v ide s t h e n e ces s a r y in t e r r u p t w h en a n e w ou t p ut w o r d is a v a i la b l e f r o m th e ad7723. dsp addr decode db15 drdy cs rd 16 16 oe d15 rd interrupt addr ad7723 74xx16374 01186-044 f i gure 44. p a r a l l e l i n ter f ac e conn ec ti o n ad7723 rev. c | page 25 of 32 serial interface the ad7723 s s e r i al da ta in t e r f ace can o p era t e in thr e e mo des, dep e ndi n g o n t h e a p plic a t ion r e q u ir e m en ts. th e t i mi n g d i a g r a m s i n fi g u r e 4 , fi g u r e 5 , a n d fi g u r e 6 s h ow h o w t h e ad7723 ma y be us ed t o tra n smi t i t s con v ersio n r e s u l t s. t a b l e 3 s h o w s t h e co n t r o l in p u ts r e q u ir ed t o s e lec t each s e r i al m o de and th e dig i tal f i l t er o p era t in g m o de. the ad7723 op era t es s o l e l y in t h e mas t er m o de , p r o v i d i n g t h re e s e r i al da t a o u t p u t pin s fo r t r a n sfer o f t h e co n v ersio n r e s u l t s. th e s e r i al da t a clo c k o u t p ut, s c o, s e r i a l d a t a o u t p u t , s d o, a n d f r a m e s y n c o u t p u t , f s o, a r e al l syn c hr o n o u s wi th clki n. f s o is co n t in uo us l y o u t p u t a t t h e co n v ersio n r a t e o f t h e a d c. s e r i a l d a t a sh i f t s out of t h e sd o pi n s y nc h ron ou s w i t h s c o . the fso is us e d t o f r a m e t h e o u t p ut da t a t r a n s m is sio n t o an ext e r n al de vi ce . an o u t p u t da t a t r a n smis sio n is ei t h er 16 o r 32 sc o c y cles in d u ra t i o n (s e e t a ble 3). s e r i al da t a s h if ts o u t o f t h e s d o p i n, ms b f i rs t, ls b last, fo r a d u ra t i on o f 1 6 sc o c y c l es. i n s e r i al m o de 1, s d o o u t p u t s 0s fo r th e las t 16 s c o c y c l es o f th e 32-c y c l e da t a t r a n smis sio n f r am e . the clo c k fo r m a t p i n, cfm t , s e le c t s t h e ac t i v e e d g e o f sc o . w i th c f mt t i ed l o g i c l o w , th e s e ri a l i n t e rf a c e o u t p u t s f s o a n d s d o cha n g e st a t e o n t h e s c o r i sin g e d g e and ar e valid on t h e f a ll i n g ed g e o f sco . w i th c f m t set h i g h , fs o a n d s d o cha n g e s t a t e on t h e fal l i n g sc o e d g e an d a r e val i d o n t h e sc o ri s i n g ed g e . the f r a m e sy n c in p u t, fs i, can be us e d if t h e ad7723 co n v ersio n p r o c es s m u s t be sy nc hr o n ize d t o an ext e r n al s o ur ce. fs i al lo ws t h e c o n v ersio n da t a p r es en t e d t o t h e s e r i al in t e r f ace to b e a f i l t er e d and de ci ma te d r e su l t der i ve d f r o m a k n o w n po i n t in tim e . a co m m o n f r a m e s y n c s i gn al ca n be a p p l i e d t o tw o o r m o r e ad7723s t o syn c hr o n ize t h em t o a co mm o n master clo c k. w h en fs i is a pplie d fo r t h e f i rst t i m e , t h e dig i t a l f i l t er s e q u en cer co u n t e r is r e s et t o 0, th e ad7723 in ter r u p t s th e c u r r en t da t a t r an smis sio n , re lo ads t h e o u t p u t s h if t r e g i s t er , r e s ets sc o , and t r a n smi t s t h e c o n v ersio n r e s u lt . s y n c hr o- niza t i on s t a r ts i m m e dia t e l y and t h e fol l o w in g c o n v ersio n s a r e in va li d w h i l e t h e dig i t a l f i l t er s e t t les. f s i can b e a p plie d o n c e a f t e r p o w e r - u p , o r i t ca n be a p e r i o d ic sig n a l , sy n c hr on o u s t o clki n, o c c u r r i n g e v er y 32 clkin c y cles. s u b s e q uen t fs i in p u ts a p pl ie d e v er y 32 clkin c y cles do n o t al ter t h e s e r i al da t a t r a n s m is si o n a nd do n o t res et t h e dig i t a l f i l t er s e q u e n c e r co un t e r . fs i is an o p t i o n a l s i g n a l ; if syn c hr o n iz a t io n is n o t r e q u ir ed , fs i can b e tie d t o a lo g i c lo w an d t h e ad7723 g e n e ra t e s fso ou t p u t s. i n s e r i al m o de 1, th e co n t r o l in p u t, s f m t , can be us e d t o s e lec t th e f o rm a t f o r th e se rial d a t a tra n s m i s s i o n (se e f i g u r e 4). fso i s ei t h er a p u ls e, a p p r o x ima t e l y o n e s c o c y cle in d u ra t i on, o r a s q ua r e wa ve wi t h a p e r i o d o f 32 sc o c y cles. w i t h a log i c lo w le v e l on s f mt , fso p u ls es hig h fo r o n e sc o c y cle a t t h e be g i n n i n g o f a da ta tra n sm i s s i o n f r a m e . w i th a logi c h i gh lev e l o n s f mt , fso g o es lo w a t t h e beg i nnin g o f a da ta tra n s m is sio n f r ame a n d re tu r n s h i g h af te r 1 6 s c o c y cl e s . n o t e t h a t in s e r i al m o de 1, fs i ca n be us e d t o s y n c hr o n ize t h e ad7723 if s f m t is s e t t o a log i c hig h . i f s f mt is s et lo w , t h e fs i in p u t has no ef fe c t o n syn c hr o n iza t io n. i n s e r i a l m o de 2 a nd s e r i a l m o de 3, s f mt sh ou ld b e t i e d hig h . ts i and d o e sh o u ld b e t i e d lo w in t h es e m o des. th e fso is a p u ls e , a p p r o x ima t e l y on e s c o c y cle in d u r a t i o n , o c c u r r in g a t th e b e gi nn i n g o f th e se rial d a t a tra n s m i s s i o n . two-channel multiplexed oper ation t w o ad di ti o n al seri al i n t e rfa c e co n t r o l p i n s , d o e a n d t s i, a r e p r o v ided t o al lo w t h e s e r i al da t a o u t p u t s o f tw o ad7723s, t o e a si ly s h a r e o n e s e r i al da t a li n e w h en op era t i n g in s e r i al m o de 1. f i gur e 45 s h o w s t h e conn ec t i o n dia g ram. s i n c e a s e r i al da t a t r a n s m is si o n f r a m e las t s 3 2 sc o c y cles, tw o ad cs can s h a r e a s i n g le da ta lin e b y al t e r n a t i n g tra n s m i s s i o n o f th ei r 16- bit output d a t a on to on e sd o pi n . ad7723 master ad7723 slave fsi sfmt tsi fsi clkin doe cfmt sdo sco fso clkin tsi cfmt sfmt doe sdo sco fso dv dd dv dd dgnd dgnd from control logic to host processor 01186-045 f i g u re 45. s e ri al m o de 1 conn ec t i on f o r t w o - chann e l m u lt ipl e x e d o p e r at io n the da t a o u t p u t ena b le p i n, d o e, co n t r o ls th e s d o o u t p u t b u f f er . w h e n t h e log i c le v e l o n d o e ma t c h e s t h e st a t e o f t h e ts i pin, t h e s d o o u t p ut b u f f er dr i v es t h e s e r i a l da t a l i n e ; o t h e r w is e , t h e ou t p ut o f t h e b u f f er g o es hig h i m p e dan c e . th e s e r i al f o r m a t p i n, s f m t , is s e t hig h t o c h o o s e t h e f r a m e sy n c o u t p ut fo r m a t . the clo c k fo r m a t p i n, cfm t , is s et lo w s o t h a t s e r i al da t a is made a v a i l a b l e o n s d o a f t e r t h e r i sin g edg e o f sc o an d ca n b e la tch e d o n t h e sc o fa l l i n g e d ge. ad7723 rev. c | page 26 of 32 the mast er de vice is s e lec t ed b y s e t t in g ts i t o a log i c lo w a nd co nn ec t i n g i t s f s o t o d o e. the s l a v e de vic e is s e lec t e d wi th i t s t s i pin t i e d h i g h an d b o t h i t s f s i a nd d o e con t r o l l e d f r o m t h e mas t er s fso . si n c e t h e fso o f t h e mas t er co n t rols t h e d o e in p u t o f b o t h t h e mas t er and s l a v e , o n e ad c s sd o is ac t i v e w h i l e t h e o t h e r is hig h im p e dance (f igur e 46). w h en t h e master t r a n smi t s i t s con v ersio n r e s u l t d u r i n g t h e f i rs t 16 sc o c y c l es o f a da t a t r a n smis s i o n f r a m e , t h e l o w le ve l o n d o e s ets t h e s l a v e s s d o h i g h im pe d a n c e . on ce t h e m a s t e r co m p let e s tra n s m i t ti n g i t s co n v e r s i o n da ta , i t s fso g o es h i gh a n d tri g g e r s th e s l a v e s fs i t o beg i n i t s da t a t r a n smis sio n f r a m e. since fso p u ls e s a r e ga t e d b y t h e r e le as e o f fs i (g o i n g lo w) an d t h e fs i o f t h e s l a v e de vice is he l d hig h d u r i n g i t s da t a t r a n smis sio n , t h e fso f r o m t h e mas t er de v i ce m u s t b e us e d fo r c o n n e c ti o n t o th e h o s t p r oc e s so r . clkin fsi sco fso (master) fsi (slave) doe (master and slave) sdo (master) sdo (slave) d1 d0 d15 d14 d15 d14 d1 d0 t 11 t 12 t 13 t 9 t 15 t 16 t 16 t 15 01186-046 f i g u re 46. s e ri al m o de 1 ti ming f o r t w o - chann e l m u lt i p lex e d o p er at io n ad7723 rev. c | page 27 of 32 serial interface to dsps i n s e r i al mo de , th e ad7723 can b e dir e c t l y in ter faced t o s e v e r a l ind u st r y -st a ndar d dig i t a l sig n a l p r o c ess o rs. i n a l l cas e s, t h e ad7723 o p era tes as the mas t er wi th t h e ds p op era t in g as t h e s l a v e . th e ad7723 p r o v ides i t s o w n s e r i al c l o c k (sco) t o tra n s m i t t h e di gi tal w o r d o n t h e s d o p i n t o t h e d s p . th e ad7723 als o g e n e ra t e s t h e f r a m e sy n c hr o n iza t io n sig n al t h a t syn c hr o n izes t h e tra n sf er o f th e 16-b i t w o r d f r o m t h e ad7723 to t h e ds p . d e p e nding o n t h e s e r i a l m o de us e d , sc o has a f r eq ue n c y eq ual t o c l k i n o r eq ual t o c l k i n / 2. w h en sco eq uals 19.2 m h z, t h e ad7723 c a n b e in t e r f ace d t o th e analog de vices ads p -2106x s h ar c ds p . w i t h a 19. 2 mh z mas t er c l o c k an d s c o eq ual t o clki n/2, t h e ad7723 ca n be in t e r f aced wi t h th e ads p -21xx fa mil y o f ds p s , th e ds p56002, a nd t h e t m s32 0 c5x-57. w h en th e ad7723 is us ed in t h e h a l f _ p w r m o d e , tha t i s , clk i n i s le s s th a n 10 mh z , t h en th e ad7723 can b e us ed wi th ds p s , s u c h as t h e t m s320c20/tms320c25 a nd th e ds p56000/ds p56001. ad7723 to adsp-21xx interface f i gur e 47 sh o w s t h e in t e r f ace b e tw e e n t h e a d sp -21xx a nd t h e ad7723. the ad7723 is o p era t ed in m o de 2 s o tha t sc o = clki n/2. f o r t h e ads p -21xx, t h e b i ts i n t h e s e r i al p o r t co n t rol r e g i s t er sh o u ld b e s et u p as rfsr = 1 (a f r a m e s y n c is n e e d e d f o r eac h tra n sf e r ), s l en = 15 (16-b i t w o r d length s), rfsw = 0 ( n or m a l f r am i n g mo d e f o r re c e ive op e r a t i o ns ) , i n v r f s = 0 (ac t i v e hi g h rf s), irfs = 0 (ext er nal rfs), and iscl k = 0 (ext er n a l ser i al c l o c k). dr rfs sclk adsp-21xx sdo fso sco ad7723 01186-047 f i g u re 47. a d 7 7 2 3 to a d s p - 21x x in ter f ac e ad7723 to sharc interface the in t e r f ac e b e tw een t h e ad7 723 a nd t h e ads p -2106x s h ar c ds p is t h e s a m e as sh o w n i n f i gur e 47 , b u t t h e ds p is co nf igur ed as f o l l o w s: s l en = 1 5 (16-b i t w o r d t r a n sf er s), se n d n = 0 ( t h e m s b of t h e 1 6 - bit word i s re c e ive d b y t h e d s p f i r s t), i c lk = 0 (a n ext e r n al s e r i al c l o c k is us e d ), rfs r = 0 (a f r a m e s y n c i s r e q u i r ed f o r ev e r y w o r d tra n s f e r ), ir fs = 0 (th e r e cei v e f r a m e sy n c sig n al is ext e r n al), ckre = 0 (t h e r e cei v e da ta i s la t c h e d in t o t h e ds p o n th e fallin g c l oc k ed g e ), l a fs = 0 ( t h e d s p b e g i n s r e a d i n g th e 1 6 - b i t w o r d a f t e r th e d s p h a s iden t i f i e d t h e f r a m e sy n c s i g n al ra t h er t h a n t h e ds p r e adin g t h e w o r d a t t h e s a me in st a n t as t h e f r a m e sy n c sig n a l is iden t i f i e d ), a nd lrfs = 0 (rfs is ac ti v e hig h ). th e ad77 23 ca n be us e d in m o de 1, m o de 2, o r m o de 3 w h en in t e r f ace d to th e ads p - 2106x s h ar c ds p . ad7723 to dsp56002 interface f i gur e 48 sh o w s th e ad7723 t o ds p56002 in t e r f ace . t o in t e r f ace t h e ad7723 t o the ds p56002, the ad c is o p era t ed in m o de 2 w h e n t h e ad c is o p er a t e d w i t h a 19.2 mh z clo c k. the ds p56002 is conf igur ed as f o l l o w s: s y n = 1 (syn c h r o n o us m o d e ), scd1 = 0 (rfs is a n in p u t), gck = 0 (a co n t in uo us s e r i al c l o c k is us ed), sckd = 0 (th e s e r i al c l o c k is ext e r n al), wl1 = l , wl0 = 0 (tra n s f e rs is 16 b i t s wide), f s l1 = 0, a nd fs l0 = 1 (th e f r a m e sy n c is ac tiv e a t t h e b e g i nnin g o f eac h tra n sf er). al t e r n a t i v e l y , t h e ds p56002 ca n be o p era t e d in asyn c h r o n o us m o de (s yn = 0 ) . i n t h i s mo de, t h e s e r i al clo c k fo r t h e r e cei v e s e c t io n is i n p u t t o t h e s c o pin. this is acco m p li sh e d b y s e t t in g bi t scd o t o 0 (ext er n a l rx c l o c k). sdr sc1 sck dsp56002 sdo fso sco ad7723 01186-048 f i gur e 4 8 . ad77 23 t o dsp5 60 02 int e r f a c e ad7723 to tms320c5x interface f i gur e 49 sh o w s th e ad7723 t o t m s320c5x in ter face . f o r th e t m s320c5x, fs r a nd cl kr ar e a u t o ma tic a l l y co nf igur ed as in p u ts. the s e r i al p o r t is co nf igur ed as f o l l o w s: fo = 0 (16-b i t w o r d t r a n sfers) a nd fs m = 1 (a f r a m e sy n c o c c u rs fo r e a c h tra n s f e r ). dr fsr clkr tms320c5x sdo fso sco ad7723 01186-049 f i g u re 49. a d 7 7 2 3 to tm s 3 20c 5x int e r f ac e ad7723 rev. c | page 28 of 32 groundi ng a nd layout the a n alog an d dig i tal p o w e r s u p p lies t o t h e ad7723 a r e inde p e n d e n t and s e p a r a tely p i n n e d o u t to m i n i mi ze co u p li n g bet w een t h e a n alog a n d d i g i tal secti o n s wi th in th e d e v i ce . th e ad7723 a g nd a nd d g nd p i ns s h o u l d be s o lder ed dir e c t l y t o a g r o u nd plan e to min i mi ze s e r i es i n d u c t an ce. i n a d d i t i on, t h e a c p a t h f rom a n y supply pi n or re f e re nc e pi n ( r e f 1 and r e f 2 ) th r o u gh i t s d e co u p l i n g ca pa c i t o r s t o i t s a s socia t ed gr o u n d m u s t b e made as sh o r t as p o s s i b l e (f i g ur e 50). t o achie v e t h e b e s t de co u p ling, pl ace s u r f ace - m o u n t c a p a ci t o rs as clos e as p o s s i b l e t o t h e de vi ce , i d e a l l y r i g h t u p a g a i n s t t h e de vice p i n s . al l g r o u nd p l anes m u s t n o t o v erla p t o a v o i d ca p a ci ti v e co u p ling. th e ad7723 s dig i t a l a nd a n alog g r o u nd p l an es m u s t b e co nn e c t e d a t o n e pl ace b y a l o w i n d u c t an ce p a t h , p r efera b ly r i g h t u nder t h e de vic e . t y p i cal l y , t h is co nn e c t i o n is ei t h er a t r ace o n t h e p r i n t e d cir c ui t b o ar d o f 0.5 cm w i de w h e n t h e g rou nd p l a n e s a r e on t h e s a me l a y e r , or 0 . 5 c m w i d e m i n i m u m pla t e d t h r o u g h h o les w h e n t h e g r o u n d plan es ar e o n dif f er en t la yers. an y ext e r n al log i c co nn e c t e d t o t h e ad7 723 s h o u l d us e a g r o u nd p l an e s e p a ra t e f r o m t h e ad7723 s dig i tal g r o u n d pla n e . th e s e two dig i t a l g r o u nd pla n es sh o u ld a l s o b e co nn e c te d a t j u st o n e place. s e pa ra t e po w e r s u p p lies f o r a v dd and d v dd are a l s o h i g h ly d e s i r a bl e. t h e d i g i t a l s u pp l y pi n d v dd shou l d b e p o we re d f rom a s e p a r a te an a l o g supply , but i f ne c e s s ar y , d v dd ma y sha r e i t s po w e r co nn ectio n t o a v dd , as sh o w n i n t h e conn e c t i o n d i a g r a m in f i gur e 50. the fer r i t es a r e als o r e co mm e n de d t o f i l t er hig h f r eq uen c y sign als f r o m co rr u p tin g t h e a n alog p o w e r s u p p l y . a min i m u m e t ch te chn i q u e is gen e r a l l y b e st fo r g r o u n d pl an es beca use i t gi v e s th e bes t s h i e ld in g. n o i s e ca n b e m i ni m i z e d b y p a yin g a t t e n t ion t o t h e sys t e m la yo u t and p r e v en t i n g dif f er en t sig n als f r o m in ter f e r i n g wi th eac h o t h e r . h i g h lev e l a n alog sig n als sh o u ld b e s e p a ra t e d f r o m lo w l e v e l a n al og sig n als, a nd bo t h sh o u ld be k e p t a w a y f r o m dig i t a l sig n als. i n wa v e fo r m sa m p li n g a n d r e co n s tr ucti o n s y s t e m s , th e sa m p li n g c l oc k (clkin) is as v u ln era b le to n o i s e as an y a n a l og sig n a l . cl kin s h o u ld be i s o l a t ed f r o m th e a n alog a n d d i g i tal sys t e m s . f a s t swi t c h in g sig n al s lik e c l o c ks sh ou ld be s h ie lde d wi t h t h e i r a s s o c i ate d g rou n d to a v oi d r a d i a t i n g noi s e to ot he r s e c t i o ns of t h e b o a r d , and clo c k sig n a l s sh ou ld ne ver b e r o u te d n e a r t h e an a l o g i n put s . a v o i d r u nnin g dig i t a l li n e s und e r t h e de vic e as t h es e co u p le n o is e on t o t h e die . th e analog g r o u n d plan e sho u ld b e al lo w e d t o r u n un der the ad7723 t o shie ld i t f r o m n o is e co u p ling. the p o w e r s u p p l y lin e s t o t h e ad7 723 s h o u l d us e as la rg e a trace as p o ssi b le (p r e fera b l y a plan e) to p r o v id e a lo w i m p e dan c e p a t h an d re d u c e t h e e f f e c t s of g l itche s on t h e p o we r s u pply l i n e . a v o i d cr o s s o ver o f dig i t a l an d ana l o g sig n a l s. t r aces o n o p p o si t e sides o f t h e bo a r d sh ou ld r u n a t r i g h t a n g l es t o e a ch ot he r . t h i s re d u c e s t h e e f f e c t s of f e e d t h rou g h t h rou g h t h e boa r d . 5v 10 f 100nf 100nf 100nf 10nf 10nf 10nf 10nf 10nf 10 f 220nf 10nf 1 f ref2 agnd2 ref1 av dd 1 agnd1 agnd1 agnd agnd av dd av dd dv dd dgnd dgnd ad7723 analog ground plane ad7723 digital ground plane 01186- 050 28 6 39 25 26 18 17 9 10 11 21 22 23 f i gure 50. r e ference and p o w e r sup p l y d ecoup ling ad7723 rev. c | page 29 of 32 outline dimensions 0. 45 0. 30 2. 45 ma x 1. 03 0. 88 0. 73 sea t i n g pl a n e view a t o p v i ew (p i n s d o wn ) 1 33 34 11 12 23 22 44 pi n 1 13. 90 bsc s q 10. 00 bs c s q 0. 25 m i n 2.10 2.00 1.95 7 0 0.10 coplanarity view a rotated 90 ccw 10 6 2 0.23 0.11 0.80 bsc lead pitch lead width compliant to jedec standards mo-112-aa-1 f i g u re 51. 4 4 -l ead m e t r ic q u ad f l at p a ckag e [m qfp ] (s-44- 2) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature p a ckage package descri ption package outlin e ad7723bs C40c to +85c 44-lead metric quad flat package (mqfp) s-44-2 ad7723bs-reel C40c to +85c 44-lead me tric quad flat package (mqfp) s-44-2 ad7723bsz 1 C40c to +85c 44-lead metric quad flat package (mqfp) s-44-2 ad7723bsz-ree l 1 C40c to +85c 44-lead metric quad flat package (mqfp) s-44-2 eval-ad7723c b e v a l u a t i o n boar d 1 z = pb-free part. ad7723 rev. c | page 30 of 32 notes ad7723 rev. c | page 31 of 32 notes ad7723 rev. c | page 32 of 32 notes ?2005 a n alo g de vices, inc. all rig h ts reserv ed. tra d ema r ks and registered tra d ema r ks are the prop erty of their respective owners . c01186C0 C 5/05(c) |
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